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FEATURES ADF4116: 550 MHz ADF4117: 1.2 GHz ADF4118: 3.0 GHz 2.7 V to 5.5 V Power Supply Separate V P Allows Extended Tuning Voltage in 3 V Systems Selected Charge Pump Currents Dual Modulus Prescaler ADF4116: 8/9 ADF4117/ADF4118: 32/33 3-Wire Serial Interface Digital Lock Detect Power-Down Mode Fast Lock Mode APPLICATIONS Base Stations for Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment
RF PLL Frequency Synthesizers ADF4116/ADF4117/ADF4118
GENERAL DESCRIPTION
The ADF4116 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and downconversion sections of wireless receivers and transmitters. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (5-bit) and B (13-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP+A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and VCO (Voltage Controlled Oscillator). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP CPGND
REFERENCE
ADF4116/ADF4117/ADF4118
REFIN 14-BIT R COUNTER 14 R COUNTER LATCH CLK DATA LE A, B COUNTER LATCH 18 13 AVDD MUX N = BP + A RFINA RFINB 13-BIT B COUNTER LOAD LOAD 5-BIT A COUNTER M3 M2 M1 FLO MUXOUT HIGH Z 21-BIT INPUT REGISTER 19 FUNCTION LATCH LOCK DETECT
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CP
SDOUT FROM FUNCTION LATCH
SDOUT
PRESCALER P/P +1
FLO SWITCH 5 CE AGND DGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ADF4116/ADF4117/ADF4118-SPECIFICATIONS1
(AVDD = DVDD = 3 V
Parameter RF CHARACTERISTICS RF Input Frequency ADF4116 ADF4117 ADF4118 ADF4118 Maximum Allowable Prescaler Output Frequency3 RF Input Sensitivity REFIN CHARACTERISTICS Reference Input Frequency Reference Input Sensitivity4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR FREQUENCY5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Reference Input Current LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD6 (AIDD + DIDD) ADF4116 ADF4117 ADF4118 IP Low-Power Sleep Mode
10%, 5 V
10%; AVDD VP 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
B Version B Chips2 Unit Test Conditions/Comments See Figure 22 for Input Circuit 45/550 0.045/1.2 0.1/3.0 0.2/3.0 165 200 -15/0 -10/0 0/100 -5/0 10 100 55 45/550 0.045/1.2 0.1/3.0 0.2/3.0 165 200 -15/0 -10/0 0/100 -5/0 10 100 55 MHz min/max GHz min/max GHz min/max GHz min/max MHz max MHz max dBm min/max dBm min/max MHz min/max dBm min/max pF max A max MHz max
Input Level = -10 dBm
AVDD, DVDD = 3 V AVDD, DVDD = 5 V AVDD = 3 V AVDD = 5 V
AC-Coupled. When DC-Coupled: 0 to VDD Max (CMOS Compatible)
1 250 2.5 1 3 2 2 0.8 x DVDD 0.2 x DVDD 1 10 100 DVDD - 0.4 0.4 2.7/5.5 AVDD AVDD/6.0 5.5 5.5 7.5 0.4 1
1 250 2.5 1 3 2 2 0.8 x DVDD 0.2 x DVDD 1 10 100 DVDD - 0.4 0.4 2.7/5.5 AVDD AVDD/6.0 4.5 4.5 6.5 0.4 1
mA typ A typ % typ nA max % typ % typ % typ V min V max A max pF max A max V min V max V min/V max V min/V max mA max mA max mA max mA max A typ
0.5 V VCP VP - 0.5 0.5 V VCP VP - 0.5 VCP = VP/2
IOH = 500 A IOL = 500 A
AVDD VP 6.0 V See Figure 20 4.5 mA Typical 4.5 mA Typical 6.5 mA Typical TA = 25C
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ADF4116/ADF4117/ADF4118
Parameter NOISE CHARACTERISTICS ADF4118 Phase Noise Floor7 Phase Noise Performance8 ADF41169 540 MHz Output ADF411710 900 MHz Output ADF411810 900 MHz Output ADF411711 836 MHz Output ADF411812 1750 MHz Output ADF411813 1750 MHz Output ADF411814 1960 MHz Output Spurious Signals ADF41169 540 MHz Output ADF411710 900 MHz Output ADF411810 900 MHz Output ADF411711 836 MHz Output ADF411812 1750 MHz Output ADF411813 1750 MHz Output ADF411814 1960 MHz Output B Version -170 -162 -89 -87 -90 -78 -85 -65 -84 -88/-99 -90/-104 -91/-100 -80/-84 -88/-90 -65/-73 -80/-86 B Chips2 -170 -162 -89 -87 -90 -78 -85 -65 -84 -88/-99 -90/-104 -91/-100 -80/-84 -88/-90 -65/-73 -80/-86 Unit dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc typ dBc typ dBc typ dBc typ dBc typ dBc typ dBc typ Test Conditions/Comments @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency Note 15 Note 15 @ 300 Hz Offset and 30 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 200 Hz Offset and 10 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency Note 15 Note 15 @ 30 kHz/60 kHz and 30 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 10 kHz/20 kHz and 10 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C. 2 The B Chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. 4 AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS-compatible levels. 5 Guaranteed by design. Sample tested to ensure compliance. 6 AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RF IN for ADF4117, ADF4118 = 900 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 8 The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). 9 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 540 MHz; N = 2700; Loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 11 fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; f RF = 836 MHz; N = 27867; Loop B/W = 3 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 1750 MHz; N = 8750; Loop B/W = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; f RF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 1960 MHz; N = 9800; Loop B/W = 20 kHz. 15 Same conditions as above. Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter t1 t2 t3 t4 t5 t6 10 10 25 25 10 20
1 (AVDD = DVDD = 3 V
10%, 5 V 10%; AVDD VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX unless otherwise noted)
Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth
Limit at TMIN to TMAX (B Version)
NOTE 1 Guaranteed by design but not production tested. Specifications subject to change without notice.
REV. 0
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ADF4116/ADF4117/ADF4118
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . -0.3 V to VP + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4C/W CSP JA Thermal Impedance (Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 122C/W (Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . . 216C/W
Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high-performance RF integrated circuit with an ESD rating of < 2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
t3
CLOCK
t4
t1
DATA DB20 (MSB) DB19
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4116/ADF4117/ADF4118 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model ADF4116BRU ADF4116BCP ADF4117BRU ADF4117BCP ADF4118BRU ADF4118BCP
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Thin Shrink Small Outline Package (TSSOP) Chip Scale Package Thin Shrink Small Outline Package (TSSOP) Chip Scale Package Thin Shrink Small Outline Package (TSSOP) Chip Scale Package
Package Option* RU-16 CP-20 RU-16 CP-20 RU-16 CP-20
*Contact the factory for chip availability.
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ADF4116/ADF4117/ADF4118
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4 5 6 7 8
Mnemonic FLO CP CPGND AGND RFINB RFINA AVDD REFIN
Function Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth. This will speed up locking of the PLL. Charge Pump Output. When enabled, this provides the ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path for the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 22. Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO. Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking the pin high will power up the device depending on the status of the power-down bit F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be accessed externally. Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.
PIN CONFIGURATIONS TSSOP Chip Scale Package
9 10 11 12 13 14 15 16
DGND CE CLK DATA LE MUXOUT DVDD VP
17 DVDD DGND 9
20 CP
CP 2 CPGND 3 AGND 4
15
DVDD MUXOUT LE
ADF4116 ADF4117 ADF4118
14 13
CPGND AGND AGND RFINB RFINA
1 2 3 4 5
DGND 10 AVDD 6 AVDD 7 REFIN 8
18 VP
FLO 1
16
VP
19 FLO
TOP VIEW RFINB 5 (Not to Scale) 12 DATA RFINA 6 AVDD 7 REFIN 8
11 10 9
ADF4116 ADF4117 ADF4118
TOP VIEW (Not to Scale)
CLK CE DGND
16 DVDD
15 MUXOUT 14 LE 13 DATA 12 CLK 11 CE
REV. 0
-5-
ADF4116/ADF4117/ADF4118-Typical Performance Characteristics
Table I. S-Parameter Data for the ADF4118 RF Input (Up to 1.8 GHz)
10dB/DIVISION -40 RL = -40dBc/Hz RMS NOISE = 0.64
FREQUNIT GHZ
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90
PARAMTYPE S AngS11
-2.0571 -4.4427 -6.3212 -2.1393 -12.13 -13.52 -15.746 -18.056 -19.693 -22.246 -24.336 -25.948 -28.457 -29.735 -31.879 -32.681 -31.522 -34.222 0.89207 0.8886 0.89022 0.96323 0.90566 0.90307 0.89318 0.89806 0.89565 0.88538 0.89699 0.89927 0.87797 0.90765 0.88526 0.81267 0.90357 0.92954
DATAFORMAT MA
0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80
KEYWORD IMPEDANCEOHMS R 50
PHASE NOISE - dBc/Hz
0.92087 0.93788 0.9512 0.93458 0.94782 0.96875 0.92216 0.93755 0.96178 0.94354 0.95189 0.97647 0.98619 0.95459 0.97945 0.98864 0.97399 0.97216 -36.961 -39.343 -40.134 -43.747 -44.393 -46.937 -49.6 -51.884 -51.21 -53.55 -56.786 -58.781 -60.545 -61.43 -61.241 -64.051 -66.19 -63.775
-50 0.64 rms -60 -70 -80 -90 -100 -110 -120 -130 -140 100Hz
FREQ MagS11
FREQ MagS11 AngS11
FREQUENCY OFFSET FROM 900 MHz CARRIER
1MHz
Figure 4. ADF4118 Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 s)
0 -5 -10
RF INPUT POWER - dBm
10dB/DIVISION -40
RL = -40dBc/Hz
RMS NOISE = 0.575
VDD = 3V VP = 3V
PHASE NOISE - dBc/Hz
-50 0.575 rms -60 -70 -80 -90 -100 -110 -120 -130
-15 -20 -25 TA = -40 C -30 -35 TA = -40 TA = -45 0 0.5 25 C 3.5 4.0 85 C
1.0 1.5 2.0 2.5 3.0 RF INPUT FREQUENCY - GHz
-140 100Hz
FREQUENCY OFFSET FROM 900 MHz CARRIER
1MHz
Figure 2. Input Sensitivity (ADF4118)
Figure 5. ADF4118 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 s)
0 -10 -20
OUTPUT POWER - dB
0
REFERENCE LEVEL = -4.2dBm
VDD = 3V, VP = 5V ICP = 1mA PFD FREQUENCY = 200kHz
OUTPUT POWER - dB
-10 -20 -30 -40 -50 -60 -70 -80 -90
REFERENCE LEVEL = -3.8dBm
VDD = 3V, VP = 5V ICP = 1mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 4
-30 -40 -50 -60 -70 -80 -90
LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 22 -90.2dBc/Hz
-91.5dBc
-100
-2kHz
-1kHz
900MHz
+1kHz
+2kHz
-100
-400kHz
-200kHz
900MHz
+200kHz
+400kHz
Figure 3. ADF4118 Phase Noise (900 MHz, 200 kHz, 20 kHz)
Figure 6. ADF4118 Reference Spurs (900 MHz, 200 kHz, 20 kHz)
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ADF4116/ADF4117/ADF4118
0 -10 -20 REFERENCE LEVEL = -4.2dBm VDD = 3V, VP = 5V ICP = 1mA PFD FREQUENCY = 200kHz OUTPUT POWER - dB LOOP BANDWIDTH = 35kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS -50 -60 -70 -90.67dBc -80 -90 -100 -400kHz -200kHz 900MHz +200kHz +400kHz AVERAGES = 10
0 -10 -20 -30 -40 -50 -60 REFERENCE LEVEL = -7.0dBm
VDD = 3V, Vp = 5V ICP = 5mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 5kHz RES. BANDWIDTH = 300Hz VIDEO BANDWIDTH = 300Hz SWEEP = 4.2ms AVERAGES = 20 -72.3dBc
OUTPUT POWER - dB
-30 -40
-70 -80 -90
-100
-60kHz
-30kHz
1750MHz
+30kHz
+60kHz
Figure 7. ADF4118 Reference Spurs (900 MHz, 200 kHz, 35 kHz)
Figure 10. ADF4118 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)
0 -10 -20 REFERENCE LEVEL = -7.0dBm
0 VDD = 3V, Vp = 5V ICP = 1mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 5kHz -10 -20 REFERENCE LEVEL = -10.3dBm VDD = 3V, Vp = 5V ICP = 1mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS -50 -60 -70 -80 -90 -400kHz -200kHz 1750MHz +200kHz +400kHz -100 -2kHz -1kHz 2800MHz +1kHz +2kHz AVERAGES = 26 -85.2dBc/Hz
OUTPUT POWER - dB
OUTPUT POWER - dB
-30 -40 -50 -60 -70
RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 25
-30 -40
-71.5dBc/Hz -80 -90 -100
Figure 8. ADF4118 Phase Noise (1750 MHz, 30 kHz, 3 kHz)
Figure 11. ADF4118 Phase Noise (2800 MHz, 1 MHz, 100 kHz)
10dB/DIVISION -40 -50
RL = -40dBc/Hz
RMS NOISE = 2.0
10dB/DIVISION -40 -50
RL = -40dBc/Hz
RMS NOISE = 1.552
2.0 rms -60 PHASE NOISE - dBc/Hz
1.55 rms -60
PHASE NOISE - dBc/Hz
-70 -80 -90 -100 -110 -120 -130 -140 100Hz
-70 -80 -90 -100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 1.75GHz CARRIER
1MHz
FREQUENCY OFFSET FROM 2.8 GHz CARRIER
1MHz
Figure 9. ADF4118 Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz)
Figure 12. ADF4118 Integrated Phase Noise (2800 MHz, 1 MHz, 100 kHz)
REV. 0
-7-
ADF4116/ADF4117/ADF4118
0 -10 -20
OUTPUT POWER - dB
-60
REFERENCE LEVEL = -9.3dBm
VDD = 3V, VP = 5V ICP = 1mA
FIRST REFERENCE SPUR - dBc
PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 3kHz VIDEO BANDWIDTH = 3kHz SWEEP = 1.4 SECONDS AVERAGES = 4 -77.3dBc
VDD = 3V VP = 5V -70
-30 -40 -50 -60 -70 -80 -90
-80
-90
-100
-2MHz
-1MHz
2800MHz
+1MHz
+2MHz
-100 -40
-20
0
20
40
60
80
100
TEMPERATURE - C
Figure 13. ADF4118 Reference Spurs (2800 MHz, 1 MHz, 100 kHz)
Figure 16. ADF4118 Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz)
-130 -135 -140
PHASE NOISE - dBc/Hz
5
FIRST REFERENCE SPUR - dBc
VDD = 3V VP = 5V
-5 -15 -25 -35 -45 -55 -65 -75 -85 -95 -105
VDD = 3V VP = 5V
-145 -150 -155 -160 -165 -170 -175
1
100 1000 10 PHASE DETECTOR FREQUENCY - kHz
10000
0
1
2
3
4
5
TURNING VOLTAGE
Figure 14. ADF4118 Phase Noise (Referred to CP Output) vs. PFD Frequency
Figure 17. ADF4118 Reference Spurs (200 kHz) vs. VTUNE (900 MHz, 200 kHz, 20 kHz)
-60 VDD = 3V VP = 5V
PHASE NOISE - dBc/Hz PHASE NOISE - dBc/Hz
-60 VDD = 3V VP = 5V
-70
-70
-80
-80
-90
-100 -40
-20
0
20
40
60
80
100
-90
0
20
40
60
80
100
TEMPERATURE - C
TEMPERATURE - C
Figure 15. ADF4118 Phase Noise vs. Temperature (900 MHz, 200 kHz, 20 kHz)
Figure 18. ADF4118 Phase Noise vs. Temperature (836 MHz, 30 kHz, 3 kHz)
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ADF4116/ADF4117/ADF4118
-60 VDD = 3V VP = 5V -70
3.0
FIRST REFERENCE SPUR - dBc
2.5
2.0
DIDD - mA
0 20 40 60 80 100
-80
1.5
1.0
-90
0.5
-100
0.0
0
50
100
150
200
TEMPERATURE - C
PRESCALER OUTPUT FREQUENCY - MHz
Figure 19. ADF4118 Reference Spurs vs. Temperature (836 MHz, 30 kHz, 3 kHz)
Figure 20. DIDD vs. Prescaler Output Frequency (ADF4116, ADF4117, ADF4118)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
A AND B COUNTERS
The reference input stage is shown below in Figure 21. SW1 and SW2 are normally-closed switches. SW3 is normally-open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL 100k TO R COUNTER BUFFER SW3 NO
The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 200 MHz or less.
Pulse Swallow Function
NC REFIN NC SW1
The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P x B) + A] x fREFIN/R fVCO P Output Frequency of external voltage controlled oscillator (VCO). Preset modulus of dual modulus prescaler. Preset Divide Ratio of binary 13-bit counter (3 to 8191). Preset Divide Ratio of binary 5-bit swallow counter (0 to 31).
SW2
Figure 21. Reference Input Stage
RF INPUT STAGE
B A
The RF input stage is shown in Figure 22. It is followed by a 2stage limiting amplifier to generate the CML clock levels needed for the prescaler.
BIAS GENERATOR 500 RFINA RFINB 1.6V AVDD 500
fREFIN Output frequency of the external reference frequency oscillator. R Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be divided down to produce the input clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
N = BP + A
AGND
Figure 22. RF Input Stage
PRESCALER (P/P + 1)
13-BIT B COUNTER FROM RF INPUT STAGE PRESCALER P/P + 1 LOAD LOAD 5-BIT A COUNTER
TO PFD
The dual modulus prescale (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized, (N = PB + A). The dual-modulus prescaler takes the CML clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9 for the ADF4116, and set to 32/33 for the ADF4117 and ADF4118. It is based on a synchronous 4/5 core. REV. 0 -9-
MODULUS CONTROL
Figure 23. A and B Counters
ADF4116/ADF4117/ADF4118
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
DVDD
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 24 is a simplified schematic. The PFD includes a fixed delay element which sets the width of the antibacklash pulse. This is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level.
VP UP CHARGE PUMP
ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT SDOUT
MUX
CONTROL
MUXOUT
DGND
Figure 25. MUXOUT Circuit
Lock Detect
HI
D1 U1
Q1
R DIVIDER CLR1
MUXOUT can be programmed for two types of lock detect: Digital Lock Detect and Analog Lock Detect. Digital Lock Detect is active high. It is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected it is high with narrow low-going pulses.
CP DELAY U3
CLR2 HI D2 U2 N DIVIDER Q2
DOWN
INPUT SHIFT REGISTER
CP GND
R DIVIDER
N DIVIDER
CP OUTPUT
The ADF4116 family digital section includes a 21-bit input shift register, a 14-bit R counter and a-bit N counter, comprising a 5-bit A counter and a 13-bit B counter. Data is clocked into the 21-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs DB1, DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table VII. Table II shows a summary of how the latches are programmed.
Table II. C2, C1 Truth Table
Figure 24. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4116 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2 and M1 in the function latch. Table VI shows the full truth table. Figure 25 shows the MUXOUT section in block diagram form.
Control Bits C2 C1 0 0 1 1 0 1 0 1
Data Latch R Counter N Counter (A and B) Function Latch Initialization Latch
-10-
REV. 0
ADF4116/ADF4117/ADF4118
Table III. ADF4116 Family Latch Summary REFERENCE COUNTER LATCH
LOCK DETECT PRECISION
TEST MODE BITS
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB20 LDP
DB19 T4
DB18 T3
DB17 T2
DB16 T1
DB15 R14
DB14 R13
DB13 R12
DB12 R11
DB11 R10
DB10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
AB COUNTER LATCH
CP GAIN
CONTROL BITS
13-BIT B COUNTER
5-BIT A COUNTER
DB20 G1
DB19 B13
DB18 B12
DB17 B11
DB16 B10
DB15 B9
DB14 B8
DB13 B7
DB12 B6
DB11 B5
DB10 B4
DB9 B3
DB8 B2
DB7 B1
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
FUNCTION LATCH
RESERVED RESERVED FASTLOCK MODE FASTLOCK ENABLE PD POLARITY COUNT RESETER
DB2 F1
POWERDOWN 2
RESERVED
TIMER COUNTER CONTROL
MUXOUT CONTROL
POWERDOWN 1
CP THREESTATE
CONTROL BITS
DB20 X
DB19 PD2
DB18 X
DB17 X
DB16 X
DB15 TC4
DB14 TC3
DB13 TC2
DB12 TC1
DB11 F6
DB10 X
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB1 C2 (1)
DB0 C1 (0)
INITIALIZATION LATCH
RESERVED RESERVED FASTLOCK MODE FASTLOCK ENABLE PD POLARITY COUNT RESETER
DB2 F1
POWERDOWN 2
RESERVED
TIMER COUNTER CONTROL
MUXOUT CONTROL
POWERDOWN 1
CP THREESTATE
CONTROL BITS
DB20 X
DB19 PD2
DB18 X
DB17 X
DB16 X
DB15 TC4
DB14 TC3
DB13 TC2
DB12 TC1
DB11 F6
DB10 X
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB1 C2 (1)
DB0 C1 (1)
REV. 0
-11-
ADF4116/ADF4117/ADF4118
Table IV. Reference Counter Latch Map
LOCK DETECT PRECISION
TEST MODE BITS
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB20 LDP
DB19 T4
DB18 T3
DB17 T2
DB16 T1
DB15 R14
DB14 R13
DB13 R12
DB12 R11
DB11 R10
DB10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
R14 0 0 0 0 * * * 1 1 1 1
R13 0 0 0 0 * * * 1 1 1 1
R12 0 0 0 0 * * * 1 1 1 1
********** ********** ********** ********** ********** ********** ********** ********** ********** ********** ********** **********
R3 0 0 0 1 * * * 1 1 1 1
R2 0 1 1 0 * * * 0 0 1 1
R1 1 0 1 0 * * * 0 1 0 1
DIVIDE RATIO 1 2 3 4 * * * 163 80 163 81 163 82 163 83
TEST MODE BITS SHOULD BE SET TO 0000 FOR NORMAL OPERATION
LDP 0 1
OPERATION 3 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 5 CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
-12-
REV. 0
ADF4116/ADF4117/ADF4118
Table V. AB Counter Latch Map
CP GAIN
13-BIT B COUNTER
5-BIT A COUNTER
CONTROL BITS
DB20 G1
DB19 B13
DB18 B12
DB17 B11
DB16 B10
DB15 B9
DB14 B8
DB13 B7
DB12 B6
DB11 B5
DB10 B4
DB9 B3
DB8 B2
DB7 B1
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
A5 X X ADF4116 * * X X
A4 X X * * X X
A3 0 0 * * 1 1
A2 0 0 * * 1 1
A1 0 1 * * 0 1
A COUNTER DIVIDE RATIO 0 1 * * 6 7 A COUNTER DIVIDE RATIO 0 1 2 * * 29 30 31
A5 0 0 ADF4117/ADF4118 0 * * 1 1 1
A4 0 0 0 * * 1 1 1
A3 0 0 0 * * 1 1 1
A2 0 0 1 * * 0 1 1
A1 0 1 0 * * 1 0 1
B13 0 0 0 0 * * * 1 1 1 1
B12 0 0 0 0 * * * 1 1 1 1
B11 0 0 0 0 * * * 1 1 1 1
********** ********** ********** ********** ********** ********** ********** ********** ********** ********** ********** **********
B3 0 0 0 1 * * * 1 1 1 1
B2 0 1 1 0 * * * 0 0 1 1
B1 1 0 1 0 * * * 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED 3 4 * * * 8188 8189 8190 8191
LDP 0 1
CURRENT SETTINGS 250 A 1mA N = BP + A, P IS PRESCALER VALUE. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF NX FREF, NMIN IS (P2-P).
REV. 0
-13-
ADF4116/ADF4117/ADF4118
Table VI. Function Latch Map
RESERVED
RESERVED
FASTLOCK MODE
FASTLOCK ENABLE
PD POLARITY
RESERVED
TIMER COUNTER CONTROL
MUXOUT CONTROL
COUNT RESETER
DB2 F1
POWERDOWN 2
POWERDOWN 1
CP THREESTATE
CONTROL BITS
DB20 X
DB19 PD2
DB18 X
DB17 X
DB16 X
DB15 TC4
DB14 TC3
DB13 TC2
DB12 TC1
DB11 F6
DB10 X
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB1 C2 (1)
DB0 C1 (0)
F1 0 1 CE PIN PD2 PD1 0 1 1 1 X X 0 1 X 0 1 1 MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN M3 0 0 0 0 1 1 M2 0 0 1 1 0 0 M1 0 1 0 1 0 1
COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET OUTPUT
THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT AVDD R DIVIDER OUTPUT ANALOG LOCK DETECT (N CHANNEL OPEN DRAIN) SERIAL DATA OUTPUT (INVERSE POLARITY OF SERIAL DATA INPUT) DGND
1 1 F2 0 1 F3 0 1 F4 0 1 1 TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F6 X 0 1 FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63
1 1
0 1
PD POLARITY NEGATIVE POSITIVE
CHARGE PUMP OUTPUT NORMAL 3-STATE
-14-
REV. 0
ADF4116/ADF4117/ADF4118
Table VII. Initialization Latch Map
RESERVED
RESERVED
FASTLOCK MODE
FASTLOCK ENABLE
PD POLARITY
RESERVED
TIMER COUNTER CONTROL DB15 TC4 DB14 TC3 DB13 TC2 DB12 TC1
MUXOUT CONTROL DB6 M3 DB5 M2 DB4 M1
COUNT RESETER
DB2 F1
POWERDOWN 2
POWERDOWN 1
CP THREESTATE
CONTROL BITS DB1 C2 (1) DB0 C1 (1)
DB20 X
DB19 PD2
DB18 X
DB17 X
DB16 X
DB11 F6
DB10 X
DB9 F4
DB8 F3
DB7 F2
DB3 PD1
F1 0 1 M3 CE PIN PD2 PD1 0 1 1 1 X X 0 1 X 0 1 1 MODE 0 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 M2 M1
COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET OUTPUT
THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT AVDD R DIVIDER OUTPUT ANALOG LOCK DETECT (N CHANNEL OPEN DRAIN) SERIAL DATA OUTPUT (INVERSE POLARITY OF SERIAL DATA INPUT) DGND
1 1 F2 0 1 F3 0 1 F4 0 1 1 TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F6 X 0 1 FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63
1 1
0 1
PD POLARITY NEGATIVE POSITIVE
CHARGE PUMP OUTPUT NORMAL THREE-STATE
REV. 0
-15-
ADF4116/ADF4117/ADF4118
THE FUNCTION LATCH Fastlock Mode Bit
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table VI shows the input data format for programming the Function Latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is "1," the R counter and the A, B counters are reset. For normal operation this bit should be "0." Upon powering up, the F1 bit needs to be disabled, the N counter resumes counting in "close" alignment with the R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB11 of the Function Latch is the Fastlock Mode bit. When Fastlock is enabled, this bit determines which Fastlock Mode is used. If the Fastlock Mode bit is "0" then Fastlock Mode 1 is selected and if the Fastlock Mode bit is "1," then Fastlock Mode 2 is selected. If Fastlock is not enabled (DB9 = "0"), then DB11 (ADF4116) determines the state of the FLO output. FLO state will be the same as that programmed to DB11.
Fastlock Mode 1
DB3 (PD1) and DB19 (PD2) on the ADF4116 family, provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asynchronous power-down, the device powers down immediately after latching a "1" into bit PD1, with the condition that PD2 has been loaded with a "0." In the programmed synchronous power-down, the device power down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a "1" into bit PD1 (on condition that a "1" has also been loaded to PD2), then the device will go into power-down after the first successive charge pump event. When a power down is activated (either synchronous or asynchronous mode including CE-pin-activated power down), the following events occur: All active dc current paths are removed. The R, N and timeout counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital clock detect circuitry is reset. The RFIN input is debiased. The oscillator input buffer circuitry is disabled. The input register remains active and capable of loading and latching data.
MUXOUT Control
In the ADF4116 family, the output level of FLO is programmed to a low state and the charge pump current is switched to the high value (1 mA). FLO is used to switch a resistor in the loop filter and ensure stability while in Fastlock by altering the loop bandwidth. The device enters Fastlock by having a "1" written to the CP Gain bit in the N register. The device exits Fastlock by having a "0" written to the CP Gain bit in the N register.
Fastlock Mode 2
In the ADF4116 family, the output level of FLO is programmed to a low state and the charge pump current is switched to the high value (1 mA). FLO is used to switch a resistor in the loop filter and ensure stability while in Fastlock by altering the loop bandwidth. The device enters Fastlock by having a "1" written to the CP Gain bit in the N register. The device exits Fastlock under the control of the Timer Counter. After the timeout period determined by the value in TC4-TC1, the CP Gain bit in the N register is automatically reset to "0" and the device reverts to normal mode instead of Fastlock. Timer Counter Control In the ADF4116 family, the user has the option of switching between two charge pump current values to speed up locking to a new frequency. When using the Fastlock feature with the ADF4116 family, the normal sequence of events is as follows: The user must make sure that Fastlock is enabled. Set DB9 of the ADF4116 family to "1." The user must also choose which Fastlock Mode to use. As discussed in the previous section, Fastlock Mode 2 uses the values in the Timer Counter to determine the timeout period before reverting to normal mode operation after Fastlock. Fastlock Mode 2 is chosen by setting DB11 of the ADF4116 family to "1." The user must also decide how long they want the high current (1 mA) to stay active before reverting to low current (250 A). This is controlled by the Timer Counter Control Bits DB14 to DB11 (TC4-TC1) in the Function Latch. The truth table is given in Table VI. Now, when the user wishes to program a new output frequency, they can simply program the A, B counter latch with new values for A and B. At the same time they can set the CP Gain bit to a "1," which sets the charge pump 1 mA for a period of time determined by TC4-TC1. When this time is up, the charge pump current reverts to 250 A. At the same time the CP Gain Bit in the A, B Counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency again.
The on-chip multiplexer is controlled by M3, M2, M1 on the ADF4116 family. Table VI shows the truth table.
Phase Detector Polarity
DB7 (F2) of the function latch sets the Phase Detector Polarity. When the VCO characteristics are positive this should be set to "1." When they are negative it should be set to "0."
Charge Pump Three-State
This bit puts the charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation.
Fastlock Enable Bit
DB9 of the Function Latch is the Fastlock Enable Bit. Only when this is "1" is Fastlock enabled.
-16-
REV. 0
ADF4116/ADF4117/ADF4118
The Initialization Latch The CE Pin Method
When C2, C1 = 1, 1 then the Initialization Latch is programmed. This is essentially the same as the Function Latch (programmed when C2, C1 = 1, 0). However, when the Initialization Latch is programmed there is a additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at load point when the N counter data is latched and the device will begin counting in close phase alignment. If the Latch is programmed for synchronous power-down (CE pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. When the first N counter data is latched after initialization, the internal reset pulse is again activated. However, successive N counter loads after this will not trigger the internal reset pulse.
Device Programming After Initial Power-Up
Apply VDD. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. Program the Function Latch (10). Program the R Counter Latch (00). Program the N Counter Latch (01). Bring CE high to take the device out of power-down. The R and N counter will now resume counting in close alignment. Note that after CE goes high, a duration of 1 s may be required for the prescaler bandgap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down in order to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after VCC was initially applied.
The Counter Reset Method
Apply VDD. Do a Function Latch Load ("10" in 2 LSBs). As part of this, load "1" to the F1 bit. This enables the counter reset. Do an R Counter Load ("00" in 2 LSBs). Do an N Counter Load ("01" in 2 LSBs). Do a Function Latch Load ("10" in 2 LSBs). As part of this, load "0" to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. The counter reset method requires an extra function latch load compared to the initialization latch method.
After initially powering up the device, there are three ways to program the device.
Initialization Latch Method
Apply VDD. Program the Initialization Latch ("11" in 2 LSBs of input word). Make sure that F1 bit is programmed to "0." Then do an R load ("00" in 2 LSBs). Then do an N load ("01" in 2 LSBs). When the Initialization Latch is loaded, the following occurs: 1. The function latch contents are loaded. 2. An internal pulse resets the R, N and timeout counters to load state conditions and also three-states the charge pump. Note that the prescaler bandgap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. Latching the first N counter data after the initialization word will activate the same internal reset pulse. Successive N loads will not trigger the internal reset pulse unless there is another initialization.
REV. 0
-17-
ADF4116/ADF4117/ADF4118
APPLICATIONS SECTION Local Oscillator for GSM Base Station Transmitter SHUTDOWN CIRCUIT
Figure 26 shows the ADF4117/ADF4118 being used with a VCO to produce the LO for a GSM base station transmitter. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 . Typical GSM system would have a 13 MHz TCXO driving the Reference Input without any 50 termination. In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference divider of the ADF4117/ADF1118. The charge pump output of the ADF4117/ADF1118 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. Other PLL system specifications are given below: KD = 1 mA KV = 12 MHz/V Loop Bandwidth = 20 kHz FREF = 200 kHz N = 4500 Extra Reference Spur Attenuation = 10 dB All of these specifications are needed and used to come up with the loop filter components values shown in Figure 27. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer and also drives the RF Output terminal. A T-circuit configuration provides 50 matching between the VCO output, the RF output and the RFIN terminal of the synthesizer. In a PLL system, it is important to know when the system is in lock. In Figure 26, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or lock-detect signal.
The attached circuit in Figure 27 shows how to shut down both the ADF4116 family and the accompanying VCO. The ADG702 switch goes open circuit when a Logic 1 is applied to the IN input. The low-cost switch is available in both SOT-23 and micro SOIC packages.
DIRECT CONVERSION MODULATOR
In some applications a direct conversion architecture can be used in base station transmitters. Figure 28 shows the combination available from ADI to implement this solution. The circuit diagram shows the AD9761 being used with the AD8346. The use of dual integrated DACs such as the AD9761 with specified 0.02 dB and 0.004 dB gain and offset matching characteristics ensures minimum error contribution (over temperature) from this portion of the signal chain. The Local Oscillator (LO) is implemented using the ADF4117/ ADF4118. In this case, the OSC 3B1-13M0 provides the stable 13 MHz reference frequency. The system is designed for a 200 kHz channel spacing and an output center frequency of 1960 MHz. The target application is a WCDMA base station transmitter. Typical phase noise performance from this LO is -85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is driven in single-ended fashion. LOIN is ac-coupled to ground with the 100 pF capacitor and LOIP is driven through the accoupling capacitor from a 50 source. An LO drive level of between -6 dBm and -12 dBm is required. The circuit of Figure 28 gives a typical level of -8 dBm. The RF output is designed to drive a 50 load but must be ac-coupled as shown in Figure 28. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power will be around -10 dBm.
VDD
VP 100pF
RFOUT
FREFIN
7 15 16 AVDD DVDD VP 2 1000pF 1000pF CP REFIN 8 51 FLO
3.3k 620pF
VCC VCO190-902T
100pF 18
18
0.15nF
27k
18
ADF4117/ ADF4118
10k
1.5nF
SPI-COMPATIBLE SERIAL BUS
14 CE LOCK MUXOUT CLK DETECT DATA 100pF LE 6 RFINA RFINB 5
CPGND AGND DGND
51
3
4
9
100pF
DECOUPLING CAPACITORS (10 F/10pF) ON AVDD, DVDD, VP OF THE ADF4117/ADF4118 AND ON VCC OF THE VCO190-902T HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 26. Local Oscillator for GSM Base Station
-18-
REV. 0
ADF4116/ADF4117/ADF4118
VP POWER-DOWN CONTROL VDD S VDD RFOUT 100pF 18
IN ADG702 D GND
7 15 16 AVDD DVDD VP CE FREFIN 8 REF IN CP FLO
2 1
VCC LOOP FILTER GND 10k VCO
100pF
18
18
ADF4116/ ADF4117/ ADF4118
RFINA
CPGND AGND DGND
6 5
100pF 51
RFINB
3
4
9
100pF
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 27. Local Oscillator Shutdown Circuit
0.1 F REFIO IOUTA IOUTB IBBP IBBP VOUT 100pF RFOUT
LOW-PASS FILTER
MODULATED DIGITAL DATA
AD9761 TXDAC
QOUTA FS ADJ 2k QOUTB LOW-PASS FILTER QBBP QBBP LOIN 100pF
AD8346
LOIP 100pF
OSC 3B1-13M0 RSET TCXO REFIN CP 1k 680pF 6.8nF RFINB 100pF RFINA 100pF 51 18pF VCO190-1960T 10k
18
SERIAL DIGITAL NTERFACE
ADF4118
100pF 18 18
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY.
Figure 28. Direct Conversion Transmitter Solution
INTERFACING
The ADF4116 family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA and LE control the data transfer. When LE (Latch Enable) goes high, the 24 bits which have been clocked into the input register on each rising edge of SCLK will get transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table II for the Latch Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 microseconds. This is certainly more than adequate for systems which will have typical lock times in hundreds of microseconds.
REV. 0
-19-
ADF4116/ADF4117/ADF4118
ADuC812 Interface
SCLOCK
SCLK SDATA LE
SCLK
SCLK SDATA LE CE MUXOUT (LOCK DETECT)
ADuC812
MOSI
I/O PORTS CE
ADF4116/ ADF4117/ ADF4118
ADSP-21xx
DT TFS
ADF4116/ ADF4117/ ADF4118
I/O FLAGS MUXOUT (LOCK DETECT)
Figure 29. ADuC812 to ADF4116 Family Interface
Figure 30. ADSP-21xx to ADF4116 Family Interface
On first applying power to the ADF4116 family, it needs three writes (one each to the R counter latch, the N counter latch and the initialization latch) for the output to become active. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input).
Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 21-bit latch, store the three 8-bit bytes, enable the Autobuffered mode and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Chip Scale (CP-20)
0.159 (4.05) 0.157 (4.00) 0.156 (3.95) 0.079 (2.0) REF 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) DETAIL E 0.020 (0.5) REF LEAD PITCH 0.014 (0.35)
16 15 20 1
Thin Shrink Small Outline (RU-16)
0.201 (5.10) 0.193 (4.90)
45
16 9
0.159 (4.05) 0.157 (4.00) 0.156 (3.95)
TOP VIEW
0.079 (2.0) REF
11 10 5 6
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
0.039 (1.00) 0.035 (0.90) 0.031 (0.80) SEATING 0.0079 (0.20) PLANE REF
0.0083 (0.211) 0.0079 (0.200) 0.0077 (0.195)
BOTTOM VIEW (ROTATED 180 )
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
LEAD OPTION DETAIL E
0.011 (0.275) 0.010 (0.250) 0.009 (0.225) 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) 0.0059 (0.15) REF
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
0.0059 (0.15) REF CONTROLLING DIMENSIONS ARE IN MILLIMETERS
-20-
REV. 0
PRINTED IN U.S.A.
1
8
C3767-5-4/00 (rev. 0)
Figure 29 shows the interface between the ADF4116 family and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4116 family needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written the LE input should be brought high to complete the transfer.
When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be 166 kHz.
ADSP-2181 Interface
Figure 30 shows the interface between the ADF4116 family and the ADSP-21xx Digital Signal Processor. The ADF4116 family needs a 21-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated.

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